This invention relates to the field of telephone switching, and more particularly to a digital switch array of the type used, for example, in PABXs (Private Automated Branch Exchanges).
Digital switches such as the Mitel DX-8980 or LDX-90820 are used in PABXs. Such switches are used to switch channels between time slots on input and output ST-buses, typically making up the rows and columns of the array respectively.
An ST-Bus is a high speed synchronous serial bus. The ST-Bus signals include a Frame Pulse (FP), a Clock (CK), and input and output ST streams. Depending on the application, the aggregate rate of the ST-Bus can be 2.048, 4.096, or 8.192 M bit/sec. Each stream is divided into frames, each frame having a period of 125 .mu.s, for a frame rate of 8000 frames/sec (8 KHz). The start of each frame is indicated by the framing signal FP. Each frame is divided into an integer number of bit periods, with bit timing provided by the clock signal (CK).
A DS (digital switch) chip will typically switch 256 channels or 8 ST-bus streams. In order to increase the number of channels, the chips are arranged in an array with the input streams divided amongst the rows and the output streams divided amongst the columns. For example, a 2.times.2 array will switch 512 channels with 8 ST-bus input streams to each row and 8 ST-bus output streams to each column. Such a Ds chip is described in detail in the Mitel Corporation Digital communication Handbook.
Each chip is addressable and contains a connection memory which is written to by a controlling microprocessor through a data input. For example, if it is desired to connect channel 7 on input stream 3, which is associated with the first row of DS chips to channel 4 on output stream 12, which is associated with the second column of chips, the control microprocessor must address the chip in position (2,2) and write to the appropriate location in the connection memory. However, it must first clear the memory location for channel 4, stream 12 in the chip in position (1,2) to prevent two chips from trying to drive the same output timeslot on the same stream and thereby corrupt the data. Thus, setting up a connection involves at least two operations, clearing the memory location in the chip in the same row that will not set up the connection, and subsequently writing to the memory location in the active chip.
This mechanism thus guarantees that only one DS chip drives a particular time slot within a column. Each DS chip contains a connection memory, which includes a separate location for each output channel. For every output channel in the connection memory, each DS chip contains an enable bit for each output timeslot that is used to enable that DS to drive a particular output timeslot. This bit is disabled (output is in high-impedance state) when the DS is not required to drive that particular time slot. The microprocessor thus programs all DS chips and makes sure that there is no conflict, that is, only one DS within a column drives a particular output timeslot. The microprocessor must maintain a memory map of which switch is active for each channel.
A further problem with this prior art approach is that a software problem (i.e. software bug or abnormal behaviour when a fault occurs), can create a situation where two or more DS chips within a column attempt to drive a particular output timeslot. This situation corrupts the data on that particular channel, increases the power dissipation of the device, and also reduces the reliability of the DS chips. This problem is hard to detect and may become the cause of a silent failure.
Another problem occurs on start-up. All DS connection memory locations are written to by the control microprocessor and all output time slots are disabled (high-impedance state). Assuming the ST-Bus streams operate at 2.048 Mbps, this requires M * N * 32 software write operations. If the ST-Bus streams operate at 8.192 Mbps, M * N * 128 software write operations are needed, where M is the number of rows and N is the number of columns.
There is also a need for a monitor software program that constantly checks the connection memory and makes sure that only one DS within a column is enabled to drive a particular output timeslot.
The current approach is slow and requires software overhead to check the integrity of the program within the DS.
On object of this invention is alleviate the aforementioned problems of the prior art.